In advanced integrated circuit technology, device dimensions are scaled down. Especially, after the gate stacks are formed, the interlayer dielectric material is difficult to fill in the gaps between the gate stacks due to the high aspect ratio of the gaps and gap-filling capability of the existing process. Although various deposition technologies are employed to form interlayer dielectric (ILD) with improved gap-filling capability, the top surface of the ILD is still uneven, resulting in tungsten residue left on the surface of the ILD after the tungsten plugs are formed in the ILD. Therefore, an interlayer dielectric structure and a method making the same are needed to address the above issue.